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Senior FPGA Engineer (Algo)

DRW · Chicago, IL · $150,000–$250,000 a year · Algo Technology & Software Engineering

Posted Sep 15, 2026 · We last checked this listing on Oct 6, 2026

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Likely interview questions for this role

Written from this job description, not a generic list. Each one notes what the interviewer is really checking.

About your past

Tell me about a latency improvement you made in hardware. How did you measure it?

What they are checking: Real low-latency results backed by careful measurement rather than estimates.

Describe a hard hardware bug you tracked down in the lab.

What they are checking: Debugging skill with tools like logic analyzers and simulation when problems only appear in hardware.

What would you do

You'd build an FPGA application from scratch for an existing trading team. How would you approach the first few months?

What they are checking: Ability to scope requirements, plan architecture and deliver incrementally on a greenfield project.

Your design fails timing closure late in the project. What do you do?

What they are checking: Practical experience with timing problems and the tradeoffs used to resolve them.

How would you work with traders who want to change strategy parameters frequently?

What they are checking: Designing for configurability so traders are not blocked by long hardware build cycles.

About the work

Walk me through the path of a market data packet from the wire to a trading decision on an FPGA.

What they are checking: Deep understanding of low-latency network parsing and decision logic in hardware.

How do you design the interface between FPGA logic and the host software?

What they are checking: Strong grasp of software and hardware interaction, which the posting stresses directly.

How do you approach block-level and system-level verification for a trading design?

What they are checking: Rigorous testing discipline, since hardware bugs in trading can be costly and hard to find.

How do you decide what logic belongs in the FPGA and what should stay in software?

What they are checking: Judgment about flexibility, latency and development cost when splitting work.

How do you make sure risk checks implemented in hardware are correct?

What they are checking: Seriousness about safety controls in hardware where mistakes can cause fast losses.

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The full job description

As published by DRW.

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk. Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets. We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus. We are currently seeking a  FPGA Enginee r to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design. This role is for the Chicago office only. Responsibilities:  • Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up • Research and evaluate a variety of cutting-edge FPGA hardware and technologies • Propose creative solutions to overcome FPGA/hardware limitations • Liaise directly with software and other design teams • Conduct lab debugging and characterization of new hardware Candidate Requirements:  • Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience) • Solid Hardware Engineering experience, especially with FPGA • Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production • Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation • Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog • Experience in FPGA design flow including synthesis, place & route , static timing analysis is required • Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required • Knowledge of the TCP/IP stack • Strong working knowledge of either XILINX or ALTERA FPGA design flow • Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus. • Excellent research and data gathering skills The annual base salary range for this position is $150,000 to $250,000 depending on the candidate’s experience, qualifications, and relevant skill set. The position is also eligible for an annual discretionary bonus. In addition, DRW offers a comprehensive suite of employee benefits including group medical, pharmacy, dental and vision insurance, 401k (with discretionary employer match), short and long-term disability, life and AD&D insurance, health savings accounts, and flexible spending accounts. For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice . California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice . #LI-BL1

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